Tutorials

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Program at a Glance
Main Tutorials (Wednesday,​ October 21, 2020)

[Tutorial 1] (13:00~14:30, Grand Ballroom 1​)

Joo-Young Kim Professor, Korea Advanced Institute of Science and Technology (KAIST)​, Korea

Title of Tutorial: AI Accelerators for Cloud Datacenters

Abstract:  

Machine learning (ML) and artificial intelligence (AI) technology are revolutionizing many fields of study in computer science as well as a wide range of industry sectors such as information technology, mobile communication, automotive, and manufacturing. As more industries are adopting the technology, we are facing an ever-increasing demand for a new type of hardware that enables faster and more energy efficient processing for AI workloads. For cloud datacenters, which receive all kinds of workloads from a number of users, the demand for a new AI hardware is even higher as it directly affects the total cost of operation. Over the last few years, traditional hardware makers such as Intel and Nvidia as well as start-up companies such as Graphcore and Habana Labs have been trying to offer the best computing platform for complex AI workloads in datacenters. In this talk, I will briefly describe the challenges of datacenter infrastructure with the case of Microsoft Catapult and review the latest AI accelerators for cloud datacenters.

Speaker’s Biography:  

Joo-Young Kim received the B.S., M.S., and Ph. D degree in Electrical Engineering from Korea Advanced Institute of Science and Technology (KAIST), in 2005, 2007, and 2010, respectively. He is currently an Assistant Professor in the School of Electrical Engineering at KAIST. He is also the Director of AI Semiconductor Systems (AISS) research center. His research interests span various aspects of hardware design including VLSI design, computer architecture, FPGA, domain specific accelerators, hardware/software co-design, and agile hardware development. Before joining KAIST, Joo-Young was a Senior Hardware Engineering Lead at Microsoft Azure working on hardware acceleration for its hyper-scale big data analytics platform named Azure Data Lake. Before that, he was one of the initial members of Catapult project at Microsoft Research, where he deployed a fabric of FPGAs in datacenters to accelerate critical cloud services such as machine learning, data storage, and networking.
Joo-Young is a recipient of the 2016 IEEE Micro Top Picks Award, the 2014 IEEE Micro Top Picks Award, the 2010 DAC/ISSCC Student Design Contest Award, the 2008 DAC/ISSCC Student Design Contest Award, and the 2006 A-SSCC Student Design Contest Award. He serves as Associate Editor for the IEEE Transactions on Circuits and Systems I: Regular Papers (2020-2021).

[Tutorial 2] (14:30~16:00, Grand Ballroom 1​)

Kyomin Sohn Master, Samsung Electronics​, Korea

Title of Tutorial: 3D-Stacked DRAM and 2.5D Heterogenous Integration Technologies for AI and HPC

Abstract:  

Advances in 3D-stacked DRAM technology has been essential in today's High-Performance Computing (HPC) and AI applications. HBM (high bandwidth memory) DRAM can provide unparalleled high bandwidth by ultra-wide IO utilizing 3D-stacked DRAMs with TSV technology. However, there are many challenges in realizing systems with these technologies like power density, thermal dissipation, testability and reliability of 3D-DRAM stacking in 2.5D configuration. In this talk, various state-of-the-art 2.5D/3D integration techniques are introduced such as chip partitioning, die-to-die interface, through-silicon-via (TSV) signaling, power delivery, and thermal considerations. Using 8-Hi/12-Hi 3D-stacked HBM2E as a practical example, Generic design strategies and considerations for 2.5D and 3D stacked IC ranging are also discussed from power-efficient design techniques and performance optimization methods to stacked-die bit-cell reliability and design for testability.

Speaker’s Biography: 

Kyomin Sohn received the B.S. and M.S. degrees in Electrical Engineering in 1994 and 1996, respectively, from Yonsei University, Seoul. From 1996 to 2003, he was with Samsung Electronics, Korea, involved in SRAM Design Team. He designed various kinds of high-speed SRAM for external cache and buffer memory. He received the Ph.D. degree in Electrical Engineering and Computer Science in 2007 from KAIST, Daejeon, Korea. He rejoined Samsung Electronics in 2007, where he has been involved in DRAM Design Team. He is a Master (Technical VP) in Samsung and he is responsible for future architecture and circuit technology of DRAMs including HBM(high bandwidth memory) DRAM. His interests include the next generation 3D-DRAM, reliable memory design, and processing-in-memory for artificial intelligence applications. In addition, he has currently served as a Technical Program Committee member of Symposium on VLSI Circuits since 2012.


[Tutorial 3] (16:00~17:30, Grand Ballroom 1)

Jerald Yoo Professor, National University of Singapore, Singapore

Title of Tutorial: Low-Noise, Low-Power Wearable Sensor Interface Circuit Design

Abstract:

Internet of Things (IoT) and healthcare applications provide attractive opportunities for the semiconductor sector. In both fields, the target is to gather data from multiple sensor nodes with minimal power consumption while maintaining low noise operation. However, designing a sensor interface circuit for such applications is challenging due to its harsh environment. Also, in such cases, the trade-off between available resources and performance among the components both in analog front-end and in the digital back-end is crucial.

This lecture will cover the design strategies of sensor interface circuits. Starting from a basic op-amp, we will first explore the difficulties, limitations, and potential pitfalls in sensor interface, and strategy to overcome such issues. Low noise operation leads to two dynamic offset compensation techniques, auto-zeroing, and chopper stabilization. After that, system-level considerations for better key metrics such as energy efficiency will be introduced. Several state-of-the-art instrumentation amplifiers that emphasize on different parameters will also be discussed. We will then see how the signal analysis part impacts the analog sensor interface circuit design. The lecture will conclude with interesting aspects and opportunities that lie ahead.


Speaker’s Biography:  

Jerald Yoo (S’05-M’10-SM’15) received the B.S., M.S., and Ph.D. degrees in the Department of Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2002, 2007, and 2010, respectively.
From 2010 to 2016, he was with the Department of Electrical Engineering and Computer Science, Masdar Institute, Abu Dhabi, United Arab Emirates, where he was an Associate Professor. From 2010 to 2011, he was also with the Microsystems Technology Laboratories (MTL), Massachusetts Institute of Technology (MIT) as a visiting scholar. Since 2017, he has been with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, where he is currently an Associate Professor. He has pioneered researches on low-energy body-area-network (BAN) transceivers and wearable body sensor networks using the planar-fashionable circuit board for a continuous health monitoring system. He authored book chapters in Biomedical CMOS ICs (Springer, 2010) and in Enabling the Internet of Things—From Circuits to Networks (Springer, 2017). His current research interests include low-energy circuit technology for wearable bio-signal sensors, flexible circuit board platform, BAN transceivers, ASIC for piezoelectric Micromachined Ultrasonic Transducers (pMUT) and System-on-Chip (SoC) design to system realization for wearable healthcare applications.
Dr. Yoo is an IEEE Circuits and Systems Society (CASS) Distinguished Lecturer (2019-2020). He also served as the IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturer (2017-2018). He is the recipient or a co-recipient of several awards: the IEEE International Symposium on Circuits and Systems (ISCAS) 2015 Best Paper Award (BioCAS Track), ISCAS 2015 Runner-Up Best Student Paper Award, the Masdar Institute Best Research Award in 2015 and the IEEE Asian Solid-State Circuits Conference (A-SSCC) Outstanding Design Award (2005). He was the Vice Chair of IEEE SSCS United Arab Emirates (UAE) Chapter. Currently, he serves as a Technical Program Committee Member of the IEEE International Solid-State Circuits Conference (ISSCC), ISSCC Student Research Preview (co-chair), IEEE Custom Integrated Circuits Conference (CICC, Emerging Technologies Subcommittee Chair), and IEEE Asian Solid-State Circuits Conference (A-SSCC, Emerging Technologies and Applications Subcommittee Chair). He is also an Analog Signal Processing Technical Committee Member of IEEE Circuits and Systems Society. He is a senior member of IEEE.


Short Tutorials (Friday,​ October 23, 2020)

[Short Tutorial 1] (12:00~12:40, Grand Ballroom 1)

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Jongsun Park Professor, Korea University, Korea

Title of Tutorial: Low Power Deep Learning Accelerator for Inferencing and Training

Abstract:

Deep neural networks (DNN) have been showing very impressive performance in a variety of tasks including image classification, object detection and speech recognition. As recent DNNs adopt deeper and larger network architectures for improved accuracy, larger computation resources and memory capacities are needed for both inference and training of such large DNNs. Although low power deep learning accelerator design has been of interest in Cloud computing, it is becoming even more critical issue as many applications are trying to run large DNNs on resource-constrained edge computing devices. This tutorial will review various low energy techniques for DNN, especially convolutional neural network (CNN) inference/training accelerator design. The tutorial first introduces the basic operations of CNN inference/training, and explains how the low power design approaches can be applied to those basic operations.

 

Speaker’s Biography:

Jongsun Park received the B.S. degree in electronics engineering from Korea University, Seoul, Korea, in 1998 and the M.S. and Ph.D. degrees in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2000 and 2005, respectively. He joined the Electrical Engineering faculty of Korea University, Seoul, Korea, in 2008. He was with the Digital Radio Processor System Design Group, Texas Instruments, Dallas, TX, USA, in 2002. From 2005 to 2008, he was with the Signal Processing Technology Group, Marvell Semiconductor Inc., Santa Clara, CA, USA. His research interests focus on variation-tolerant, low-power, high-performance VLSI architectures and circuit designs for deep learning and digital signal processing.


[Short Tutorial 2] (12:00~12:40, Lily 1)


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Jaeduk Han Professor, Hanyang University, Korea

Title of Tutorial: Analog Circuit Design Techniques in Advanced CMOS Technologies

Abstract:

As the CMOS technology scales down below 100 nm, structures, device characteristics, and design rules related to the scaled transistors get complicated, and traditional design methodologies based on quadratic device models are not directly applicable. This leads to recent design methods relatively unsystematic; many analog designs are implemented and sized based on previous designs and/or iterative simulations with trial-and-errors. These simulation-and-intuition-based approaches often fail to provide systematic procedures that produce optimal designs for given specifications and topologies. Therefore, the classical design methodologies need to be revisited and improved to enable more systematic implementations of analog circuit designs. This tutorial introduces a design methodology based on normalized parameters such as transconductance efficiency (gm/ID), and their effectiveness in finding optimum sizing parameters to meet target specifications, while capturing complicated device and layout dependent parameters. Several circuit design examples are demonstrated to help designers practice and utilize the new methodology. In addition to the methodologies, circuit design techniques specific to advanced CMOS processes are presented as well.

 

Speaker’s Biography:

Jaeduk Han received his B.S. and M.S. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, in

2007, and 2009, respectively, and Ph.D. degree in Electrical Engineering and Computer Sciences from University of California at Berkeley, CA, USA, in 2017. He has held various internship and full-time positions at TLI, Altera, Intel, Xilinx, and Apple, where he worked on digital, analog, and mixed-signal integrated circuit designs and design automation. In 2019, he joined Hanyang University as an assistant professor. His research interests include high-speed analog and mixed-signal

(AMS) circuit design and automation.