[Tutorial 1] (13:00~14:30, Grand Ballroom 1)
Joo-Young Kim Professor, Korea Advanced Institute of Science and Technology (KAIST), Korea
Title of Tutorial: AI Accelerators for Cloud Datacenters
Kyomin Sohn Master, Samsung Electronics, Korea
Title of Tutorial: 3D-Stacked DRAM and 2.5D Heterogenous Integration Technologies for AI and HPC
Advances in 3D-stacked DRAM technology has been essential in today's High-Performance Computing (HPC) and AI applications. HBM (high bandwidth memory) DRAM can provide unparalleled high bandwidth by ultra-wide IO utilizing 3D-stacked DRAMs with TSV technology. However, there are many challenges in realizing systems with these technologies like power density, thermal dissipation, testability and reliability of 3D-DRAM stacking in 2.5D configuration. In this talk, various state-of-the-art 2.5D/3D integration techniques are introduced such as chip partitioning, die-to-die interface, through-silicon-via (TSV) signaling, power delivery, and thermal considerations. Using 8-Hi/12-Hi 3D-stacked HBM2E as a practical example, Generic design strategies and considerations for 2.5D and 3D stacked IC ranging are also discussed from power-efficient design techniques and performance optimization methods to stacked-die bit-cell reliability and design for testability.
Kyomin Sohn received the B.S. and M.S. degrees in Electrical Engineering in 1994 and 1996, respectively, from Yonsei University, Seoul. From 1996 to 2003, he was with Samsung Electronics, Korea, involved in SRAM Design Team. He designed various kinds of high-speed SRAM for external cache and buffer memory. He received the Ph.D. degree in Electrical Engineering and Computer Science in 2007 from KAIST, Daejeon, Korea. He rejoined Samsung Electronics in 2007, where he has been involved in DRAM Design Team. He is a Master (Technical VP) in Samsung and he is responsible for future architecture and circuit technology of DRAMs including HBM(high bandwidth memory) DRAM. His interests include the next generation 3D-DRAM, reliable memory design, and processing-in-memory for artificial intelligence applications. In addition, he has currently served as a Technical Program Committee member of Symposium on VLSI Circuits since 2012.
Jerald Yoo Professor, National University of Singapore, Singapore
Title of Tutorial: Low-Noise, Low-Power Wearable Sensor Interface Circuit Design
Internet of Things (IoT) and healthcare applications provide attractive opportunities for the semiconductor sector. In both fields, the target is to gather data from multiple sensor nodes with minimal power consumption while maintaining low noise operation. However, designing a sensor interface circuit for such applications is challenging due to its harsh environment. Also, in such cases, the trade-off between available resources and performance among the components both in analog front-end and in the digital back-end is crucial.
Short Tutorials (Friday, October 23, 2020)
[Short Tutorial 1] (12:00~12:40, Grand Ballroom 1)
Jongsun Park Professor, Korea University, Korea
Title of Tutorial: Low Power Deep Learning Accelerator for Inferencing and Training
Deep neural networks (DNN) have been showing very impressive performance in a variety of tasks including image classification, object detection and speech recognition. As recent DNNs adopt deeper and larger network architectures for improved accuracy, larger computation resources and memory capacities are needed for both inference and training of such large DNNs. Although low power deep learning accelerator design has been of interest in Cloud computing, it is becoming even more critical issue as many applications are trying to run large DNNs on resource-constrained edge computing devices. This tutorial will review various low energy techniques for DNN, especially convolutional neural network (CNN) inference/training accelerator design. The tutorial first introduces the basic operations of CNN inference/training, and explains how the low power design approaches can be applied to those basic operations.
Jongsun Park received the B.S. degree in electronics engineering from Korea University, Seoul, Korea, in 1998 and the M.S. and Ph.D. degrees in electrical and computer engineering from Purdue University, West Lafayette, IN, in 2000 and 2005, respectively. He joined the Electrical Engineering faculty of Korea University, Seoul, Korea, in 2008. He was with the Digital Radio Processor System Design Group, Texas Instruments, Dallas, TX, USA, in 2002. From 2005 to 2008, he was with the Signal Processing Technology Group, Marvell Semiconductor Inc., Santa Clara, CA, USA. His research interests focus on variation-tolerant, low-power, high-performance VLSI architectures and circuit designs for deep learning and digital signal processing.
Jaeduk Han Professor, Hanyang University, Korea
Title of Tutorial: Analog Circuit Design Techniques in Advanced CMOS Technologies
As the CMOS technology scales down below 100 nm, structures, device characteristics, and design rules related to the scaled transistors get complicated, and traditional design methodologies based on quadratic device models are not directly applicable. This leads to recent design methods relatively unsystematic; many analog designs are implemented and sized based on previous designs and/or iterative simulations with trial-and-errors. These simulation-and-intuition-based approaches often fail to provide systematic procedures that produce optimal designs for given specifications and topologies. Therefore, the classical design methodologies need to be revisited and improved to enable more systematic implementations of analog circuit designs. This tutorial introduces a design methodology based on normalized parameters such as transconductance efficiency (gm/ID), and their effectiveness in finding optimum sizing parameters to meet target specifications, while capturing complicated device and layout dependent parameters. Several circuit design examples are demonstrated to help designers practice and utilize the new methodology. In addition to the methodologies, circuit design techniques specific to advanced CMOS processes are presented as well.
Jaeduk Han received his B.S. and M.S. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, in
2007, and 2009, respectively, and Ph.D. degree in Electrical Engineering and Computer Sciences from University of California at Berkeley, CA, USA, in 2017. He has held various internship and full-time positions at TLI, Altera, Intel, Xilinx, and Apple, where he worked on digital, analog, and mixed-signal integrated circuit designs and design automation. In 2019, he joined Hanyang University as an assistant professor. His research interests include high-speed analog and mixed-signal