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Main Tutorials (Wednesday, October 25, 2023)
[Main Tutorial] 13:00~14:30
A Comprehensive Study on the Design Methodology of Level Shifter Circuit and its Applications

Dr. Yongfu Li
(Associate Professor, Department of Micro and Nano Electronics, Shanghai Jiao Tong University, China)
Biography Abstract

Yongfu Li (S’09–M’14-SM’18) received the Ph.D. degrees from the Department of Electrical and Computing Engineering, National University of Singapore (NUS), Singapore.

He is currently an Associate Professor with the Department of Micro and Nano Electronics Engineering and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University, China. He was a research engineer with NUS, from 2013 to 2014. He was a senior engineer (2014-2016), principal engineer (2016-2018) and member of technical staff (2018-2019) with GLOBALFOUNDRIES, as a Design-to-Manufacturing (DFM) Computer-Aided Design (CAD) research and development engineer.

He has involved in different roles in many prestigious IEEE CASS conferences (ISCAS, ISICAS, AICAS, NEWCAS, ISVLSI, ASP-DAC, and APCCAS) and regional activities. He has organized several special sessions and issues in IEEE CASS Journals and Conferences. Currently, he is serving as the IEEE CASS Board of Governors (Young Professionals), IEEE CASS Publication Division members, IEEE CASS Women in CAS – Young Professionals (WiCAS-YP) Steering Committee and IEEE CASS Digital Communications AdHoc Committee.

Multi-supply-voltage (MSV) technique is ubiquitously used to reduce power consumption in system-on-chips (SoCs). When a signal propagates across different voltage domains, an additional circuit is required to convert the signal voltage to the correct voltage level at the receiving voltage domain. Level shifting the signal voltage to a lower voltage domain can be simply resolved with a buffer circuit; However, shifting the signal voltage to a higher voltage is more challenging. Thus, a level shifter (LS) circuit is used to provide these signal interface. The aggressive scaling down in supply voltage has demanded LS circuits with an ultra-low input voltage of ≤200mV while maintaining the output range for the I/O devices of 1.8-3.0V. Therefore, designing an ultra-low input voltage LS with a wide voltage range has been a great challenge in low-power applications. These designs aim to achieve one or more of these multiple design goals, such as minimize peak current, static power consumption, dynamic power consumption, number of stages, area, maximize output swing, and avoid floating node. This tutorial aims to help our readers to get involved with the state-of-the-art and challenges of this rapidly growing field.


Short Tutorial (Wednesday, October 25, 2023)
[Short Tutorial 1] 14:30~15:10
Recent Trend in Computing-in-Memory: Analog vs. Digital

Prof. Tony Tae-Hyoung Kim
(Associate Professor, Nanyang Technological University, Singapore)
Biography Abstract

Tony Tae-Hyoung Kim (Senior Member, IEEE) received the B.S. and M.S. degrees in electrical engineering from Korea University, Seoul, South Korea, in 1999 and 2001, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Minnesota, Minneapolis, MN, USA, in 2009. From 2001 to 2005, he was with Samsung Electronics, Hwasung, South Korea. In 2009, he joined Nanyang Technological University, Singapore, where he is currently an Associate Professor.
He has published over 200 papers in journals and conferences and holds 20 U.S. and Korean patents registered. His current research interests include computing-in-memory for machine learning, ultra-low power circuits and systems for smart edge computing, low-power and high-performance digital, mixed-mode, and memory circuit design, variation-tolerant circuits and systems, and emerging memory circuits for neural networks.
Dr. Kim received IEEE ISSCC Student Travel Grant Award in 2022 and 2019, Best Paper Award (Gold Prize) in IEEE/IEIE ICCE-Asia2021, Korean Federation of Science and Technology (KOFST) Award in 2021, Best Demo Award at APCCAS2016, Low Power Design Contest Award at ISLPED2016, Best Paper Awards at 2014 and 2011 ISOCC, AMD/CICC Student Scholarship Award at IEEE CICC2008, DAC/ISSCC Student Design Contest Award in 2008, Samsung Humantech Thesis Award in 2008, 2001, and 1999, and ETRI Journal Paper of the Year Award in 2005. He was the Chair of the IEEE Solid-State Circuits Society Singapore Chapter in 2015-2016 and is Chair-Elect/Secretary of the IEEE Circuits and Systems Society VSATC. He has served on numerous IEEE conferences as a Committee Member. He serves as a Corresponding Guest Editor for the IEEE JOURNAL on EMERGING and SELECTED TOPICS in CIRCUITS and SYSTEMS (JETCAS), a Guest Editor for the IEEE TRANSACTIONS on BIOMEDICAL CIRCUITS and SYSTEMS (TBioCAS), an Associate Editor for the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS and IEEE ACCESS.
The recent development in neural networks has required massive data transfer between memory and processing elements for data processing. This heavy data transfer leads to substantial energy overhead and limits the overall performance of the neural networks. Computing-in-memory (CIM) has attracted the research community’s attention because of the significant energy efficiency improvement by minimizing the energy-hungry data transfer. CIM designs can employ either analog computing or digital computing, while each has its pros and cons. In this talk, I will present the basics of CIM design and various challenges. After that, various state-of-the-art CIM macros will be introduced. I will also discuss analog and digital CIM macros and their applications. In the last part, I will introduce several CIM designs based on emerging non-volatile memory devices.

Motivation and Focus
The traditional von Neumann architecture struggles in processing highly data-intensive parallel operations such as deep neural networks (DNNs) and machine learning applications. The heavily frequent data transfer between processing elements and memory becomes the main bottleneck in the traditional architecture. To address the above issues, computing-in-memory (CIM) has been explored to improve the overall performance and efficiency by executing repeated computations inside memory and minimizing the data transfer. However, CIM design is not mature yet and still requires various innovations. Therefore, it is timely to understand the basics of CIM and learn recent state-of-the-art works. This tutorial will cover the basics of CIM, design challenges, and several recent works so that the audience can have an overview about CIM.

[Short Tutorial 2] 15:10~15:50
On the Development of Energy-Efficient Training Accelerators for Deep Learning

Prof. Jaeha Kung
(Associate Professor, Electrical Engineering, Korea University, Korea)
Biography Abstract

Jaeha Kung received the B.S. degree in Electrical Engineering from Korea University, Seoul, South Korea, in 2010, the M.S. degree in Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejon, South Korea, in 2012, and the Ph.D. degree in Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta, GA, USA, in 2017.
He is currently an Associate Professor at the School of Electrical Engineering, Korea University, Seoul, South Korea. Prior to joining Korea University, from 2017 to 2022, he was with the Department of Electrical Engineering and Computer Science, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu, South Korea. His current research interests include energy-efficient digital accelerators for deep learning, distributed learning systems, hardware design for artificial intelligence, and low-power VLSI design. He also serves as a Technical Committee for IEEE/ACM DAC, IEEE/ACM ISLPED, IEEE ISCAS, and IEEE AICAS.
Training deep neural networks (DNNs) is a computationally expensive job, which can take weeks or months even with high performance GPUs. As a remedy for this challenge, community has started exploring the use of more efficient data representations in the training process, e.g., FP16, bfloat16, or block floating point (BFP). Generally, DNNs are trained in IEEE single precision format, i.e., FP32, to minimize the accuracy loss during the training on CPUs/GPUs. To increase the effective arithmetic and memory bandwidth during the training, one may reduce the precision in representing activations, weights, and/or gradients. NVIDIA Tensor Cores utilize mixed precision training, multiplying two inputs in IEEE half-precision (FP16), while accumulating the results in FP32. This approach doubles the effective memory bandwidth and achieves up to 2∼4× speed up in DNN training. Instead, one may preserve the exponent bits of FP32 (8-bit) but truncate the mantissa bits to make 16-bit, i.e., bfloat16. Considering the overwhelming size of the recently developed DNNs, however, keeping all tensors in floating point representations would require huge memory footprint and significant training time. Recently, a block floating point (BFP) representation has been revived and applied in training DNNs to improve performance and energy efficiency. In this tutorial, I will cover the latest research directions in developing a highly energy efficient DNN training accelerators utilizing BFP formats. Last but not least, I will discuss how we can extend the RISC-V instruction set to support the BFP-based matrix multiplication at various BFP precisions and block sizes.
[Short Tutorial 3] 15:50~16:30
Lightweight AI Hardware Systems for Inference and Training

Prof. Seungkyu Choi
(Assistant Professor, Electronic Engineering, Kyung Hee University)
Biography Abstract

Seungkyu Choi received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 2016, 2018, and 2022, respectively.
He was a Postdoctoral Researcher with the University of Michigan, Ann Arbor, MI, USA. He is currently an Assistant Professor with the Department of Electronic Engineering at Kyung Hee University, South Korea. His research interests include VLSI implementation of accelerators for digital signal processing and designing deep learning hardware architectures.
Recently, extensive research has been dedicated to lightening the deep learning process to tackle the challenges posed by the rapid growth of model size, computational complexity, and memory bandwidth demands. With the escalation of training workloads, the lightweight AI study is not solely concentrated on inference but also underscores the significance of optimizing the training process. Unlike the lightweight AI studies based on algorithmic research, realizing the complete potential of lightweight processes in deep learning acceleration necessitates system-level optimization. This talk mainly focuses on designing the lightweight hardware system for deep learning acceleration of both inference and training. We explore various types of design methodologies to reduce the memory and computational burden of deep learning training operations. Several works covering dataflow architecture, mixed-precision MAC architecture, and approximate computing-based acceleration are introduced in the talk.
[Short Tutorial 4] 16:30~17:10
Multi-Level DC-DC Converter Design with Capacitor Voltage Balancing Technique

Prof. Se-Un Shin
(Assistant Professor, Electrical Engineering, Pohang University of Science and Technology (POSTECH), Korea)
Biography Abstract

Se-Un Shin received the B.S. degree in electronics engineering from Kyungpook National University, Daegu, South Korea, in 2013, and the integrated master’s and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2018.
From 2018 to 2019, he was with the University of Michigan, Ann Arbor, USA as a Post-Doctoral Associate. In 2023, he joined the Department of Electrical Engineering, POSTECH, Pohang, South Korea where he is currently an Assistant Professor. His current research interests include analog integrated circuit design and power management IC design, energy harvesting, battery charger, wireless power transfer systems, switched capacitor/inductive converters, and hybrid converter topology.
The demand for dc-dc converters with a high conversion gain is experiencing rapid growth, driven by the diverse requirements of various products. While traditional converters encounter challenges such as switch voltage stress and low power efficiency, a multi-level converter with a high conversion gain and low voltage rating for switches would be an ideal solution to supply the stable power. However, in practical implementation, multi-level converters encounter a concern related to flying capacitor voltage imbalances. These imbalances stem from factors like parasitic capacitance and gate driving power. Consequently, they lead to significant conduction losses in switch on-resistance, as well as inductor parasitic resistance. Additionally, there are substantial overlap losses and switch damage. To address these issues, a flying capacitor calibration technique becomes indispensable for multi-level converters.
In this tutorial, we will focus on a specific design example: our proposed three-level current mode boost converter. This design incorporates a fully state-based phase selection technique, which serves to resolve the aforementioned issues present in conventional approaches. We will delve into the advantages and fundamental operating principles that underpin multi-level converters, while showcasing how our approach provides a solution.


Mini Tutorials (Wednesday, October 25, 2023)
[Mini Tutorial 1] 17:10~17:30
High-Speed Time-Domain ADC Design

Prof. Il-Min Yi
(Assistant Professor, Electrical Engineering and Computer Science, Gwangju Institute of Science and Technology(GIST), Korea)
Biography Abstract

Il-Min Yi received the B.S., M.S., and Ph.D. degrees in Electronic and Electrical Engineering from Pohang University of Science and Technology (POSTECH), Korea, in 2008, 2010, and 2015, respectively. From 2015 to 2016, he worked as Postdoctoral researcher at POSTECH, Korea. From 2017 to 2020, he was with Device Technology Labs, NTT, Japan, where he worked on the design of high-speed ADC circuits. From 2020 to 2022, he was with Texas A&M University, USA, where he was involved in the design of high-speed electrical and optical link circuits. Since 2023, he has been with Gwangju Institute of Science and Technology (GIST), Korea, where he is an Assistant Professor. His research interests include high-speed serial/parallel links, high-speed ADC circuits, and signal integrity.
As the complexity of equalization has increased due to high channel loss in high-speed serial link design, interests in high-speed time-interleaved analog-to-digital converters (TI ADCs) for implementing digital-domain equalization has been increasing. Successive approximation register (SAR) ADC architectures are popularly used for TI ADC designs due to their low power consumption. However, their limited single-channel conversion speed necessitates a high interleaving factor. As low-power high-speed alternatives to conventional voltage-domain architectures, time-domain (TD) ADCs performing voltage-to-time-to-digital conversion have emerged. Recent TD ADC designs have achieved remarkable advancements in energy efficiency, confirming their potential as a promising solution for high-speed link requirements. To comprehend TD ADCs in this trend, this talk will introduce the operation of TD ADCs, various TD ADC designs, and essential building block circuits.
[Mini Tutorial 2] 16:50~17:10
IC Techniques for Battery Diagnosis

Prof. Junwon Jeong
(Assistant Professor, Electrical Engineering, Sookmyung Women’s University, Korea)
Biography Abstract

2008 – 2012: B.S. in Electrical Engineering, Korea University, Seoul
2012 – 2019: Ph.D. in Electrical Engineering, Korea University, Seoul

Professional Experience
2021 – present: Assistant Professor, Sookmyung Women’s University
2019 – 2021: Senior Engineer, Korea Electronics Technology Institute, Seongnam, Korea
2019 – 2019: Senior Engineer, Samsung Electronics, Hwaseong, Korea
2015 – 2016: Visiting Scholar, University of Michigan

Research Interest: Power management IC (DC-DC converter, energy harvesting, LDO), sensor readout IC (battery, CIS, magnetometer, etc.)

An accurate battery diagnosis is essential to enable safe and efficient battery utilization. Electrochemical impedance spectroscopy (EIS) is widely studied in recent years because it can separate and quantify various electrochemical reactions inside the battery. However, the implementation of EIS is limited to a discrete level, requiring integrated circuit (IC)-level implementation to alleviate the cost of EV applications. This tutorial addresses IC techniques for EIS.
[Mini Tutorial 3] 17:10~17:30
Ternary VLSI Design: A Circuits and Systems Perspective

Prof. Sunmean Kim
(Assistant Professor, School of Electronics Engineering, Kyungpook National University, Korea)
Biography Abstract

Sunmean Kim received the B.S., M.S., and Ph.D. degrees in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2016, 2018, and 2021, respectively. Since 2023, he has been an assistant professor with the School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea. From 2021 to 2023, he was a postdoctoral researcher with the CAD and SoC Design Laboratory (CSDL) in Pohang University of Science and Technology (POSTECH), Pohang, South Korea. His current research interests include circuits & systems design for emerging technologies.
Binary logic circuits have been the basis for modern computers to improve energy efficiency based on complementary metal-oxide-semiconductor (CMOS) technology. However, as the limitations of CMOS scaling are approaching, a new computing paradigm has been required. Multi-valued logic (MVL) circuits focus on minimizing hardware cost by processing more than two values per elementary operation. In recent years, various designs of three-valued (ternary) logic circuits have been proposed as the first step toward implementing MVL circuits with emerging technologies. In this presentation, I will talk about an efficient design methodology for various ternary logic circuits using emerging technologies to demonstrate the potential of a ternary microprocessor.