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Keynote Speakers

Thursday, October 26, 2023
[Keynote Speech 1] 09:35~10:15
TBD

Soon jae Won
(Vice-president, Samsung Electronics Device Solutions, Korea)

Biography Abstract

Biography
TBD
Abstract
TBD
[Keynote Speech 2] 10:15~10:55
TBD

Ben Gu
(Corporate Vice President, Cadance R&D – CPG, MSA, USA)

Biography Abstract

Biography
Ben Gu joined Cadence in 2012 and since 2018, he has led CPG’s Multiphysics System Analysis (MSA) group, which includes Voltus, Sigrity, EMX, Fidelity, Clarity, Celsius, and DCX. Previously, Ben worked in DSG, where his team developed Voltus for full chip power sign-off, which provided industry-leading capacity and performance. Under his leadership, MSA has launched numerous exciting system analysis products, including Clarity for 3D electromagnetic analysis, Celsius for electro-thermal analysis, and Optimality – Cadence’s first System Analysis AI solution. Additionally, he and his team have acquired several companies, including Numeca, Integrand, Pointwise, Future Facilities, and most recently, Cascade Technologies. Ben has articulated a compelling vision and strategy that has motivated our global team to deliver cutting-edge, high-quality solutions and customer success.
Abstract
TBD

Friday, October 27, 2023
[Keynote Speech 1] 10:25~11:05
Predictive Analytics for Advanced Computing

Dr. Rajiv Joshi
(IBM T.J. Watson Research Center, USA)

Biography Abstract

Biography
Dr. Rajiv V. Joshi is an IEEE Fellow, winner of the prestigious IEEE Daniel Noble award, and a key technical lead/Research Scientist at T. J. Watson research center, IBM. He received his B.Tech IIT (Bombay, India), M.S (MIT), and Dr. Eng. Sc. (Columbia University). He has led successfully predictive failure analytic techniques for yield prediction and also the technology-driven SRAM at IBM Server Group. His statistical techniques are tailored for machine learning and AI which are licensed and commercialized. He received 3 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for contributions in interconnect technologies, holds 70 invention plateaus, and has over 284 US patents covering front end and back end of the line processes, and structures, volatile and non-volatile memories, Compute in Memory structures, machine learning algorithms and quantum computing and over 430 international patents. He has authored and co-authored over 225 papers and given over 60 invited/keynote talks and given several Seminars. He received the NY IP Law Association “Inventor of the Year” award in Feb 2020. He received an industrial pioneer award in 2014 from IEEE Circuits and Systems Society. He received the Best Editor Award from the IEEE TVLSI journal. He is inducted into the New Jersey Inventor Hall of Fame in Aug 2014. He won the Mehboob Khan award two times from Semiconductor Research Corporation. He won several best paper awards from ISSCC 1992, ICCAD 2012, ISQED, and VMIC. He is a member of the IBM Academy of Technology and a master inventor. He serves on the Board of Governors for IEEE CAS as an industrial liaison. He serves as an IEEE CAS Ambassador to India. He served as a Distinguished Lecturer for IEEE CAS, CEDA, and EDS society. He is an ISQED and World Technology Network fellow and distinguished alumnus of IIT Bombay.
Abstract
As the technology scales, process, voltage, and temperature, variations (PVT) and model inaccuracies impact design yield. This talk highlights a predictive analytical technique based on machine learning techniques targeting both memory and custom logic design applications. Several techniques are described to overcome the problems with the conventional methodologies. For advanced technologies, we extend these techniques to enable key features such as the Front End of the Line (FEOL) and back end of the line (BEOL) parasitic extraction and TCAD for manufacturability for 16nm and below. This increases the statistical confidence in the functionality and operability of the system-on-chip as a whole. They are further extended to predict aging effects in memories and the utility of this technique is demonstrated through hardware fabrication. In addition, the talk shows the application of predictive analytics for cryo-CMOS in quantum computing.
[Keynote Speech 2] 11:05~11:45
AI: Trailblazing the Path of Semiconductor Innovation

Aiqun Cao
(Vice President, Digital Implementation, EDA Group, Synopsys, Inc., USA)

Biography Abstract

Biography
Aiqun Cao is Vice President, Engineering of EDA group at Synopsys, leading the team delivering industry leading physical design tools used for taping out the most complex and advanced chips. Prior to this role, he held various management and engineering lead roles working in different areas of multiple flagship place and route tools at Synopsys.

Aiqun Cao received his B.S. degree in Electronic Engineering and M.S. degree in Microelectronics, both from Tsinghua University, China in 1998 and 2000 respectively. He received his Ph.D. degree in Electrical and Computer Engineering from Purdue University in 2004. He has published tens of technical papers and been granted more than a dozen of patents in the physical design area.

Abstract
TBD