Keynote Speeches
Keynote Speech
1. Sung-Mo “Steve” Kang
UC Santa Cruz, USA
Title: Cognitive Systems-on-Chip for Quality of Life
Future living is difficult to predict, but it is certain that nano/microelectronics will play critical roles to help enhance the quality of life for future generations. With nanotechnology and 3D integration potential, realization of cognitive systems-on-chip is becoming tangible. On functionality side, 3D integration will bring out innovative and unique system capabilities with sensory and cognitive functions. On physical side, increasing power density and nanoscale device dimensions in integrated circuits have paused serious barriers due to leakage currents, thermal issues, reliability concerns, and I/O bottlenecks. In this talk, we will discuss system perspectives and design science innovations that can help achieve desired goals, and also new technologies that can promote vertical integration beyond chip stacking. Also discussed will be the potential of neuromorphic computing and self-adaptable SoCs based on recent memristive devices.
Sung-Mo “Steve” Kang is Distinguished Chair Professor of the University of California, Santa Cruz and Chancellor Emeritus of the University of California, Merced. From March 2007 to June 2011, he was Chancellor of University of California, Merced and Professor of Engineering, and from January 2001 to February 2007 he was Dean of Engineering and Professor of Electrical Engineering at the University of California at Santa Cruz. From August 1995 to December 2000, he served as Head of the Department of Electrical and Computer Engineering of the University of Illinois at Urbana-Champaign (UIUC). Prior to UIUC he was Supervisor of High-End Microprocessor Design at AT&T Bell Laboratories at Murray Hill and also had served as a faculty member of Rutgers University. His recent awards include the inaugural KAST Deok Myeong Engineering Award in 2010, Silicon Valley Engineering Hall of Fame Induction in 2009, Chang-Lin Tien Leadership Award in 2007, IEEE Mac Van Valkenburg CAS Society Award in 2005. He obtained his Ph.D. degree from the University of California, Berkeley in 1975, M.S. degree from the State University of New York, Buffalo in 1972, B.S. degree from Fairleigh Dickinson University, Teaneck, NJ in 1970, all in electrical engineering. He is a fellow of IEEE, ACM, AAAS and a foreign member of the National Academy of Engineering, Korea.
2. Giovanni De Micheli
EPFL Lausanne, Switzerland
Title: Nanosystems: devices, circuits, architectures and applications
Much of our economy and way of living will be affected by nanotechnologies in the decade to come and beyond. Mastering materials at the molecular level and their interaction with living matter opens up
unforeseeable horizons. This talk deals with how we will conceive, design and use nanosystems, i.e., integrated systems exploiting nanodevices. Whereas switching circuits and microelectronics have been the enablers of computer and communication systems, nanosystems have the potentials to realize innovative computational fabrics whose applications require broader hardware abstractions, extended software layers and with a much higher complexity level overall. The abstraction of computation, the nanosystem architecture, the technological feasibility envelope and the multivariate design optimization problems pose challenging and disruptive research questions that this talk will address.
Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering and of the Integrated Systems Centre at EPF Lausanne, Switzerland. He is program leader of the program. Previously, he was Professor of Electrical Engineering at Stanford University.He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).
Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea. His research interests include several htmlects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies, networks on chips and 3D integration. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 450 technical articles. His citation h-index is 70 according to Google Scholar.
Prof. De Micheli is the recipient of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received also the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000, the D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS in 1987, and several Best Paper Awards, including DAC (1983 and 1993), DATE (2005) and Nanoarch (2010). He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1987-2001). He has been Chair of several conferences, including DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989). He is a founding member of the ALaRI institute at Universita' della Svizzera Italiana (USI), in Lugano, Switzerland, where he is currently scientific counselor.
3. Dr. Chi-Ping Hsu
Sr. VP, and head of Silicon Realization Group, Cadence, USA
Title: Designing Tomorrow’s Complex SoCs
Modern electronics deliver mission-critical access to information and high-speed communications, all in completely mobile form factors. The SoCs that power these electronic devices must enable HD video, 3D imaging, and massive data manipulation while offering battery life that last days not hours. Mixed-signal, low-power, and advanced-node design technologies are advancing at a faster rate than ever before.
However, in many cases, product hardware capabilities are only baseline qualifications. Products actually compete and differentiate on the basis of the applications they can enable – whether games on a smartphone or protocols on a network router. To be successful, new designs must be optimized at the system level, as well as SoC and silicon levels.
In this session, Dr. Hsu will show how the process of electronics product realization is changing to optimize application-driven design. He will also discuss specific challenges and solutions related to escalating silicon density and design complexity.
Chi-Ping Hsu is senior vice president of research and development for the Silicon Realization Group, Cadence Design System, Inc. He is responsible for the core business that encompasses silicon design, verification and implementation, and includes signoff/DFM, package and board. Hsu previously served as chief strategist of products and technologies and corporate vice president and general manager of both synthesis solutions and digital IC implementation.
Hsu was the visionary behind the Cadence Low Power Solution and the primary driver of Power Forward, the industry’s leading initiative organization focused on enabling the development of power-efficient ICs and electronic systems. Prior to joining Cadence in 2003, Hsu served as president and chief operating officer of Get2Chip Inc. and before that held executive management positions at Avant! Corporation, where he was responsible for corporate and technology strategy, product development and marketing. Hsu holds a Ph.D. degree in EECS from the University of California, Berkeley, and a BSEE degree from National Taiwan University.
Plenary Speech
1. Liang Gee Chen
National Taiwan University, Taiwan
Title: Intelligent Electronics: new opportunity and challenge to have better life with SOC
Due to the driving of Moore’s law in semiconductor industry, the Information evolution changes most the living style of human being in the past decades. IT products are heavily used to service for enterprise, then to service for people. Every people are enjoying the convenience come from the integration of communication, computing, and interfacing technologies. What will be the next wave after much more function could be integrated into a single chip, or so called SOC? Can devices or products smart enough to help people watching all environment and making necessary actions without human’s guidance in the near future? The new opportunity and challenges come from the technology of Intelligent Electronics will be discussed during this talk.
Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor, 1981–1986, and an Associate Professor, 1986–1988, in the the Department of Electrical Engineering, National Cheng Kung University. In the military service in 1987-1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. From 1993 to 1994, he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004 to 2006, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is the General Chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology from June 1996 until now, and the Associate Editor of IEEE Transactions on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE.
2. Sungho Park
Sr. Vice President, Samsung Electronics, Korea
Title: Future SoC Design Challenges for Mobile Applications
We are in the midst of smart mobile device revolution that started with smart phones, expanding to mobile computing devices (e.g. Tablets) and to other applications that will truly alter our future living. At the center of this change is the SOC for mobile applications which is facing tremendous design challenges to deliver very high performance at low power in a relatively short time.
This talk will introduce several major technical trends that are creating the enormous challenges to SOC design and potential solutions that can deliver an optimized high performance SOC for future mobile applications.
Sungho Park is Sr. Vice President of AP Development at System LSI Division of Samsung Electronics. Sungho joined Samsung Electronics in 1996 to participate in the 21264 Alpha CPU develop with Digital Equipment Corporation in Hudson Massachusetts. In 1998, he moved to API Networks, a private company funded by Samsung and Compaq, to continue work on Alpha CPU system chip development. Later on in 2002, he moved to System LSI division in Korea as VP of Engineering responsible for development of Network processors, MCU and ASIC products.
Since 2007, he headed the AP Development, responsible for development of high performance mobile AP SOC products including the S3C6410, S5C110, and the latest Exynos series. Prior to Samsung Electronics, he worked on development of PowerPC 603, 7xx at IBM, Sparc based MCU at Fujitsu Microelectronics and various SOCs at AMD, Intel and Mostek. Sungho graduated with BSEE in 1980 from Georgia Institute of Technology and MSEE in 1984 from University of Illinois at Chicago.
3. Kunihiro Asada
VLSI Design and Education Center , University of Tokyo, Japan
Title: Solutions for Side Effect of Low Voltage Operation in Deep Sub-micron VLSI Circuits
The scaling of VLSI is going to extremely fine regions toward the final feature size. One of issues, which cause difficulties in circuit design, is the supply voltage reduction due to the device reliability view point. The supply current is, on the other hand, not reduced but tending to increase, based on the scaling rule. Both the reduction of the supply voltage and the increase in the supply current result in the side effect, the signal-to-noise ratio (S/N) degradation, as a result of IR-drop and dI/dt noises. It degrades the dynamic range in analog design and the timing fault in logic design. In this presentation, we first introduce a possibility of time-domain approaches as a solution for the analog dynamic range problem. Examples of the time domain circuits will be introduced along with Time-Domain-Amplifiers (TDA) and Time-to-Digital-Converters. We also introduce solutions for power line noise issues, mainly for logic circuits. Possibilities of active canceling methods on chips will be discussed.
Keywords-Time domain circuit, TDA, TDC, Noise cancel, Switched decap
Kunihiro Asada received the B. S., M. S., and Ph.D. from University of Tokyo in 1975, 1977, and 1980, respectively. In 1980 he joined the Faculty of Engineering, University of Tokyo. From 1985 to 1986 he stayed at Edinburgh University as a visiting scholar. From 1990 to 1992 he served as the Editor of IEICE Transactions on Electronics. In 1996 he established VDEC in University of Tokyo. He served as the Chair of IEEE/SSCS Japan Chapter in 2001-2002 and the Chair of IEEE Japan Chapter Operation Committee in 2007-2008. He is currently professor, director of VDEC. His research interest is design and evaluation of integrated systems and component devices. He is a member of IEEE, IEICE and IEEJ.
Invited Speech
Vice President, Dongbu Hitek Co., Ltd, Korea
Title: New Development Paradigm of CMOS Image Sensors in Semiconductor Foundry
Mainly thanks to the dramatic growth of mobile phone industry for the last tens of years, CMOS image sensors (CIS) have been developed and manufactured on mobile platforms where key success factors have been price competitiveness based on thinner and smaller form factors of the mobile handsets and optical performances mostly represented by low intensity characteristics and signal-to-noise ratio. However, main drawbacks of the CIS devices for mobile applications are huge amount of money for setting up miniaturized processes and thereby less chances of ROI, indicating significant potential risks from investment perspective. In contrast to these, specialized sensors have been drawing attention in that they are able to prolong the life expectancy of the CIS processes, provide differentiation of customized service to each of the special applications such as medical, security, digital still camera and automotives and add values by securing higher selling profits at least more than 3 times than those of mobile counterparts. Also, they make both convergence and diversification possible, bridging the industries of system IC, bio, medical, social security and automotives. This has been consistent with key social trend emphasizing mobile life, real time, social network and long life span. In this presentation, it is demonstrated how we are able to implement specialized sensor technologies by utilizing both existing mobile CIS processes and additional features of customized and product specific technologies.
Yoon Jong Lee is Vice President and general manager of Mixed Foundry Business Unit of Dongbu Hitek, a key semiconductor foundry service company in Korea. He is responsible for one of the two foundry business units in the company and is heading sales, marketing and process development of CMOS image sensors (CIS), mixed signal processes including RF CMOS and embedded Non Volatile Memories. He previously served as VP of process development and technology planning and successfully led the CIS process development and manufacturing on different generations of technology from 0.18um to 90nm for both mobile and specialized applications. Prior to Dongbu Hitek, he worked with Ministry of Information and Telecommunication in Korean government as a project manager to plan and manage several R&D programs on semiconductor system IC and convergence components in 2005-2007. He received the B.S. degree in electronics engineering from Seoul National University in 1984 and M.S., and Ph.D. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), in 1986, and 1994, respectively.
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