Keynote Speeches
Keynote Speech1  
High performance and low power SoC Design for IT convergence – making the impossible, possible

Mr. Keith Clarke
ARM Ltd.
Vice President and General Manager of Fabric IP, Processor Division

Keith Clarke is Vice President and General Manager of Fabric IP, Processor Division at ARM. Keith has been with ARM since 1993, initially working on ASICs and then became a part of the team that developed the ARM7TDMI processor. He has held various positions in ARM including VP Engineering and VP Technical Marketing. His current position has responsibility for the Fabric IP product line within the Processor Division. Prior to ARM, he spent three years designing ASICs for the aerospace industry. Keith graduated with a B.Eng in 1989 from Southampton University, UK. He is a Chartered Member of the IET.

The convergence of many applications leads to greater and greater expectations for the devices consumers like to buy. This talk will explore some of the key considerations for designers of the SoCs tasked with fulfilling these needs. In particular, an insatiable need for more performance with ever increasing power efficiency seems like an impossible trade off. However with the right design choices and optimisations, amazing things are possible.

Keynote Speech2  
Low Power Design Methodology: Past, Now and Future

Dr. Qi Wang
Cadence Design Systems
Engineering Director of the Synthesis Group

Dr. Qi Wang joined Cadence in 1998 and is currently Group Director of the Solutions Marketing group. In this role, he is responsible for marketing of Cadence Low-Power and Mixed-Signal solutions. Prior to this position, Dr. Wang holds various R&D positions at Cadence. He is the chief architect of Common Power Format, which was donated to Si2 and became the industry first open power format in early 2007. As the Vice Chair of the Low Power Coalition and the Chair of the Format Working Group at, he is also actively driving the industry coalition to promote advanced low power designs and methodologies. Dr. Wang holds a B.S. degree in Applied Electronics from Shanghai Jiao Tong University, an MSEE degree from Southern Illinois University and a Ph.D degree in Electrical and Computer Engineering from University of Arizona.

Low Power design has come a long way from an implementation driven methodology with mostly manual process into nowadays a more matured and automated design methodology. Have we solved all the problems yet? The answer is obviously not. The ability to improve the low power design methodology lies in how well we understand the gaps between modern advanced low power design requirements and the start-of-art low power design methodology as well as how well we foresee the evolution of low power design technology in the future. In this presentation, we will take a quick historical review on the evolution of low power design methodology followed by a thorough analysis on its impact on low power designs. We will then conclude the talk with some future directions on low power design methodology and how it can close the gaps with current low power design requirements and adapt to future advancements in low power designs.

Plenary Speech1  
Green and Smarter Semiconductor for Future Mobiles

Dr. Seung Ho Hwang
Samsung Electronics
Senior Vice President, Infrastructure Design Center

Seung Ho Hwang received B.S. degree from Seoul National University in 1979, M.S. degree from Korea Advanced Institute of Science and Technology (KAIST) in 1981, and Ph.D. degree from University of California, Berkeley in 1989 all in electrical engineering.
From 1989 to 1990 he was with Schlumberger Technologies in San Jose, CA. From 1990 to 1997 he was with KAIST as a faculty member, where he published several tens of international journal and conference papers. He worked at Silicon Image Inc. from 1996 to 2006, where he developed two de facto industry standards, Digital Visual Interface (DVI) and High-Definition Multimedia Interface (HDMI). He is the key inventor of HDMI technologies. In 2006 he joined Samsung Advanced Institute of Technology as a senior vice president and worked about one and half years and in April 2008 he moved to System LSI Division of Semiconductor Business of Samsung Electronics, where he is taking the role of Chief Technology Officer and is leading Infrastructure Design Center where major infrastructure is developed for all product developments including analog and digital IP’s, design methodologies, and ASIC designs.

Recently, the mobile device is getting smarter and more versatile. It can not only deliver powerful performance for complicated computations, but also provide multiple features for daily life use owing to advanced mobile application processors. At the same time, lower power consumption is required for longer turned-on state in mobile application processors. Moreover, it is becoming mandatory for the green earth for containing CO2 emission. Hence smarter and green must come together in future mobiles.

In this presentation, technical achievements and challenges are introduced for future mobile semiconductor. To meet the growing performance requirements, technologies for high performance and multiple functions considering the power consumption are presented. Nanometer-scale silicon technology is described as an important technology momentum. Various low power methodologies are introduced for the best watt-per-performance in logic and memory. We conclude this presentation with a perspective of the future and its challenges.

Plenary Speech2  
Dependable System against PVT and Aging Employing Self-Synchronous Operation

Prof. Makoto Ikeda
University of Tokyo
Department of Electronic Engineering

Makoto Ikeda received B.S., M.S., and Ph.D. from University of Tokyo in 1991, 1993 and 1996, respectively. In 1996 he joined the Faculty of Engineering, University of Tokyo. Since then he has been working for VLSI Design and Education Center (VDEC), University of Tokyo. He is currently an Associate Professor at VDEC, University of Tokyo. He has been technical program committee members of many international conferences including, ISSCC, VLSI Circuits Symposium, A-SSCC, COOL Chips, FPL, ICFPT, ICCAD and ISQED. He is Program committee chair of COOL Chips and ISSCC ITPC FE regional committee vice chair. His research interest includes reliable system design based on self-synchronous operation. He is a member of IEEE, IEICE, IPSJ, and ACM.

PVT (Process Voltage and Temperature) variations and aging effect have been one of the serious issues of the nano-meter CMOS process. Such variations become more serious in cases of low voltage operations such like near and below threshold operations by solar cell operations. The conventional synchronous designs hit serious wall to cope with delay fault not only during design phase, but also during operations.
This presentation shows recent results on self-synchronous systems studied in our research group, to show resilient to PVT variations and the aging effect without any delay penalty and performance tuning. Self-synchronous systems with fully completion detection circuits is one of promising candidates for the delay-fault free operations, which is adaptive to delay variations in any kinds such like PVT and aging. To achieve the fully completion detection circuits, we have been working for dual-rail dynamic logic, such like DCVSL. In this presentation, basic self-synchronous systems with DCVSL circuits and margin free operation of a simple microprocessor, fabricated in 0.18um CMOS and 90nm CMOS, is shown, and self-synchronous FPGA(SSFPGA) as one of example of self-synchronous fine grain, gate-level pipelining circuits is also shown. SSFPGA chips are designed and fabricated in 65nm CMOS and measurement results on performance variation due to PVT variations and aging. We verified correct operation even with more than 40%pp power bounce introduced into the chip.

Invited Speech1  
Bioanalytic Techniques with Silicon Chips for Human Healthcare

Prof. Donhee Ham
Harvard University
Electrical Engineering and Applied Physics

Donhee Ham is Gordon McKay Professor of Electrical Engineering and Applied Physics at Harvard University, where he is with the School of Engineering and Applied Sciences. He earned a B.S. in physics from Seoul National University, South Korea, in 1996, where he graduated summa cum laude with the Valedictorian Prize as well as the Presidential Prize, ranked top 1st across the Natural Science College, and also with the Physics Gold Medal (sole winner). Following a year and a half of mandatory service in the Korea Army, he went to Caltech for a graduate training in physics. There he worked on general relativity and gravitational astrophysics under Professor Barry Barish, and later obtained a Ph.D. in electrical engineering in 2002 winning the Charles Wilts Prize for the best thesis in Electrical Engineering. His doctoral work examined the statistical physics of electrical circuits. He was the recipient of the IBM Doctoral Fellowship, Li Ming Scholarship, IBM Faculty Partnership Award, IBM Research Design Challenge Award, Silver Medal in the National Mathematics Olympiad, and the fellow of the Korea Foundation of Advanced Studies. He shared Harvard's Hoopes prize with William Andress. He was recognized by MIT Technology Review as among the world's top 35 young innovators in 2008 (TR35), for his group's work on CMOS RF biomolecular sensor utilizing nuclear spin resonance to pursue disease screening and medical diagnostics in a low-cost, hand-held platform.

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Recent researches have shown that solid-state electronic chips can be directly interfaced with biological samples or systems in order to monitor vital signals or to analyze biomolecules. Due to the low fabrication cost and small size, the electronic chips, especially silicon integrated circuits, with such capabilities can potentially become important components in realizing the much-talked about healthcare programs such as ubiquitous healthcare and personalized medicine. I would like to review some recent developments in this area of technology, including some works in my own research group at Harvard, e.g., CMOS RF biomolecular sensors using nuclear spin resonance and silicon + electrochemistry.

Invited Speech2  
Sensing Temperature with Heat and other Cool things

Prof. Kofi K.A.A. Makinwa
Delft University
Micro-elektronica & Computer Engineering,
Elektronische Instrumentatie

Kofi A.A. Makinwa is a Professor at Delft University of Technology, The Netherlands, where he leads a group that designs precision analog circuits, ΣΔ modulators, and smart sensors. He holds B.Sc. and M.Sc. degrees from Obafemi Awolowo University, Nigeria, an M.E.E. degree from the Philips International Institute and a Ph.D. degree from Delft University of Technology, both in The Netherlands. From 1989 to 1999 he was a research scientist at Philips Research Laboratories. He holds 14 patents, has (co)-authored over 100 technical papers, and has given tutorials at the ISSCC and several other conferences. Dr. Makinwa is a (co)-recipient of JSSC, ISSCC (3), ESSCIRC, ISCAS and IEEE Sensors best paper awards, and is a recipient of the Simon Stevin Gezel award from the Dutch Technology Foundation. He is a distinguished lecturer of the IEEE and a member of the Young Academy of the Royal Netherlands Academy of Arts and Sciences.

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Temperature sensors are everywhere! They are used in CPUs for thermal management, in DRAMs to control refresh rates, and in MEMS frequency references for temperature compensation, to name a few high volume applications. Conventional temperature sensors are based on bipolar transistors, and must be trimmed to compensate for the inaccuracy (about 3C) caused by process spread. However, trimming is a time consuming process that significantly increases manufacturing costs. This talk will discuss recent research on temperature sensors based on the thermal diffusivity of silicon, i.e. the rate at which heat diffuses through silicon. Due to the purity of IC-grade silicon, such temperature sensors achieve untrimmed inaccuracies of 0.2C, which is much better than that of conventional sensors.

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