Organizers: Prof. Kyeong-Sik Min (Kookmin University, Korea)
Timetable Session Abstract
This special session showcases cutting-edge research in next-generation computing paradigms that integrate biological principles, advanced memory technologies, and neuromorphic architectures. The session features five innovative presentations that represent the forefront of computational innovation. The session opens with groundbreaking work on in-sensor computing using bidirectional photoresponses in CMOS-compatible ferroelectric field-effect transistors, demonstrating how sensing and processing can be seamlessly integrated. Following this, researchers present FeRAM-based computing solutions specifically designed for edge intelligence applications, addressing the growing demand for efficient local processing.
A particularly novel contribution explores Ising chip architectures incorporating zinc-derived topological features with sub-harmonic injection locking, offering new approaches to optimization problems. The session also covers self-referential programming techniques for speech command recognition implemented on Processing-in-Memory (PIM) inference systems, bridging traditional computing with bio-inspired methodologies. The final presentation introduces TianU, a sophisticated multimodal accelerator featuring fine-grained processing unit scheduling for enhanced inference efficiency. This work represents significant advances in parallel processing architectures.
Collectively, these presentations demonstrate the convergence of biological computing principles, emerging memory technologies, and neuromorphic design, offering attendees insights into future computing systems that promise improved efficiency, reduced power consumption, and enhanced processing capabilities for artificial intelligence and edge computing applications.
| Time | Details |
| 14:05 ~ 14:20 |
Self-Referential Programming for Speech Command Recognition on a PIM Inference SoC |
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ChoongHyun Lee, Cimang Lu Pebble Square |
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| 14:20 ~ 14:35 |
Si-Backside Side-Channel Leakage Measurement and Simulation |
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XIUYAN LI Shanghai Jiao Tong University |
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| 14:35 ~ 14:50 |
Computing in Memory using FeRAM for edge intelligence |
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Seungmyeong Cho, JS Lee, HJ Jo, D Yun, JH Moon, Kyeong-Sik Min Kookmin University |
|
| 14:50 ~ 15:05 |
TianU: A Multimodal Accelerator with Fine-Grained Processing Unit Scheduling for Efficient Inference |
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Aisen Xie1, Shouzhong Peng2, Liang Chang1 1University of Electronic Science and Technology of China |
|
| 15:05 ~ 15:20 |
An Oscillator-based Ising Chip with Zinc‑Derived Topological Architecture and Sub-harmonic Injection Locking |
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Jiaer Chen, Zhong Li, Jerald Yoo Seoul National University |
Organizers: Prof. Jae-Yoon Sim (POSTECH, Korea)
Timetable Session Abstract
The Institute of Electronics, Information and Communication Engineers (IEICE) has been the biggest institute in the areas of electrical engineering and associated fields in Japan. As one of the international collaborative activities between the IEICE and the Institute of Semiconductor Engineers (ISE) of Korea, this special session is organized to introduce research activities from the Electronic Society of IEICE and ISE in the areas of advance integrated circuit (IC) designs. It will give valuable times for exchanging technical ideas and sharing experiences on advanced topics of IC designs as well as opportunities of fruitful networking for possible international collaborations between researchers in Korea and Japan.
| Time | Details |
| 15:35 ~ 15:50 |
(Invited) Sub-1V Analog LDO Design with Feedback-Driven Optimization |
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Sung-Wan Hong Sogang University |
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| 15:50 ~ 16:05 |
(Invited) Slightly-Analog Circuit Design for Light-Weight Hardware Security |
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Noriyuki Miura The University of Osaka |
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| 16:05 ~ 16:20 |
(Invited) Scalable Multi-Core FPGA Accelerator for (2,2)-Isogeny Based PQC |
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Kosei Nakamura, Makoto Ikeda The University of Tokyo |
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| 16:20 ~ 16:35 |
(Invited) DAC/ADC-DSP-Based Wireline Transceivers for Ultra High-Speed Chip-to-Chip Interconnects |
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Gain Kim DGIST |
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| 16:35 ~ 16:50 |
(Invited) Optical Chiplet Using Device-Embedded Substrate for xPU Interconnections |
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Tadashi Minotani NTT |
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| 16:50 ~ 17:05 |
(Invited) T-REX: Hardware-Software Co-Optimized Transformer Accelerator with Reduced External Memory Access and Enhanced Hardware Utilization |
|
Seunghyun Moon Konkuk University |
Organizers: Prof. Won-Young Lee (Seoul National University of Science and Technology, Korea)
Timetable Session Abstract
In recently years, artificial intelligence (AI) is known as the core driving force of the next industrial revolution, and its applications have been advanced in many fields such as computer vision, language understanding, auto-driving, and robotics. Since AI software has grown in complexity, demands on reliable and high performance computing systems consistently are growing. Therefore, the advanced hardware and software techniques beyond von Neumann computers have been studied for AI processing platform to execute AI algorithms at reasonable speed. In this special session, five papers will discuss emerging techniques for enhancements of AI processing platforms regarding AI algorithms, processing architectures, hardware implementations and software developments.
| Time | Details |
| 08:30 ~ 08:45 |
Parallel Feature Extraction for Efficient Defect Pattern Analysis in Wafer Maps |
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Minho Choi, Taehyeon Kim, Hwajung Kim Seoul National University of Science and Technology |
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| 08:45 ~ 09:00 |
AE-Guide: Attention and Entropy Guided Visual Token Dropping for Accelerating High-Resolution Vision-Language Models |
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Gilha Lee, Hyun Kim Seoul National University of Science and Technology |
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| 09:00 ~ 09:15 |
GATHER: A Gated-Attention Accelerator for Efficient LLM Inference |
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Eunjin Lee, Eunseo Kim, Eunjoung Yoo, Jaehyeong Sim Ewha Womans University |
|
| 09:15 ~ 09:30 |
Memory-Efficient Depthwise Convolution Accelerator with Run-Length Coding |
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Chaebin Lee, Jaeseong Kim, Dayoung Lee, Seung Eun Lee Seoul National University of Science and Technology |
|
| 09:30 ~ 09:45 |
Leakage-based Temperature Sensor with Incremental Analog-to-Digital Converter |
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Yeonsu Kim, Myunghyun Jeon, Su-Hyeon Kim, Jaewon Nam Seoul National University of Science and Technology |
Organizers: Prof. Hanho Lee (Inha University, Korea)
Timetable Session Abstract
Artificial intelligence (AI) and Security are playing an increasingly crucial role in the IoT, 5G/6G, and smart mobility applications, and they have also become the fundamental components of modern intelligent society. The applications of AI, post-quantum cryptography, homomorphic encryption for IoT, 5G/6G and smart mobility need to be portable, lightweight, low-latency and high-speed to provide reliable service. Meanwhile, massive devices connected to the edge of communication networks should be post-quantum safe and secure, because emerging quantum computers can easily crack the traditional public-key ciphers. To meet the requirements of high-throughput and diverse application scenarios of next-generation communications and autonomous mobility, it is necessary to resort to configurable and low-latency algorithms and architectures of AI and security. The high-performance, low-latency domain specific architecture has become a trend of circuits and systems design in the post-Moore era, which can also be applied to the AI and security in a wide range of applications.
| Time | Details |
| 08:30 ~ 08:45 |
FPGA-Accelerated Neural Network Inference via a μkernel-Enabled Bytecode Interpreter |
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Sangcheol Park, Suhwan Park, Jin-Ku Kang Inha University |
|
| 08:45 ~ 09:00 |
Reliability Improvement of Physical Unclonable Functions with String Current Variation of 3D NAND Flash Array |
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Dayeon Yu, Hwiho Hwang, Hyungjin Kim Hanyang University |
|
| 09:00 ~ 09:15 |
Twiddle-Factor Generation Using Reused Butterfly Array for Fully Homomorphic Encryption |
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Muhammad Ogin Hasanuddin, Hanho Lee Inha University |
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| 09:15 ~ 09:30 |
Design and Evaluation of Low-Depth Approximate Quantum Computing |
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Taegyun Kim, Jungu Kang, Yeongkyo Seo Inha University |
|
| 09:30 ~ 09:45 |
An Adjustable Switched-Capacitor LDO with An Inverter-Based Charge-Pump for Fast Transient Responses |
|
Sangwoong Sim, Jungkook Jo, Jaehoon Jun Inha University |
Organizers: Prof. Hiroo Sekiya (Chiba University, Japan)
Timetable Session Abstract
TBD
| Time | Details |
| 13:20 ~ 13:35 |
Comparative Study of Physical Reservoir Computing with Periodic and Chaotic Circuits for Chaotic Time Series Prediction |
|
Ayase Ihara Tokushima University |
|
| 13:35 ~ 13:50 |
Evaluation of Memory Capacity and Performance in Oscillators Reservoir with Different Nonlinearities |
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Yasufumi Kajino, Yoko Uwate, Yoshifumi Nishio Tokushima University |
|
| 13:50 ~ 14:05 |
Chaotic Time Series Prediction via ESN with Decorrelated Reservoir Dynamics |
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Hyuga Katsura, Yoko Uwate, Yoshifumi Nishio Tokushima University |
|
| 14:05 ~ 14:20 |
Design of an electronic circuit bursting neuron model based on the concept of ergodic sequential logic neuromorphic circuit |
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Ryota Otawa, Hiroyuki Torikai Hosei University |
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| 14:20 ~ 14:35 |
An FPGA-based Ergodic Sequential Logic Spiking Neural Network for Reinforcement Learning |
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Yuki Matsushima, Hiroyuki Torikai Hosei University |
Organizers: Prof. Ka Lok Man (Xi’an Jiaotong-Liverpool University, China)
Timetable Session Abstract
DATICS workshops/special sessions were initially created by a network of researchers and engineers both from academia and industry in the areas of Design, Analysis and Tools for Integrated Circuits and Systems (DATICS). The proposed DATICS-ISOCC’25 special session will focus on emerging Circuits and Systems (CAS) topics that will strongly lead human life revolutions, especially in CMOS technologies, communication technologies and biomedical technologies. Human life revolutions come along with economic opportunities. The market for these emerging topics is also forecast to grow to a multi-billion dollar market in the coming decade. The special session will highlight the potential and current developments of these CAS topics, along with pressing challenges. The proposed session is coherent and complementary to the conference theme and areas of interest of ISOCC. The main target of DATICS-ISOCC’25 is to bring together engineering researchers and people from industry to exchange theories, ideas, techniques and experiences. In addition, DATICS Yearly Special Session has been carried out at ISOCC since 2012.
| Time | Details |
| 13:20 ~ 13:35 |
Pipelined and RNS Implementations of Fibonacci Q-matrix based Encryption/Decryption Circuits Design |
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Tso-Bing Juang, Huang-Sen Chiu National Pingtung University |
|
| 13:35 ~ 13:50 |
Standard and High-Voltage MOS Class-E Power Amplifier Design |
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Roberto Cancelli, Gianfranco Avitabile Politecnico di bari |
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| 13:50 ~ 14:05 |
A Multi-Level Simulation Framework of RIS Circuit Non-Idealities |
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Stefano Lioce1, Ka Lok Man2, Gianfranco Avitabile3 1Centre Inria d’Université Côte d’Azur |
|
| 14:05 ~ 14:20 |
Street Detection Gaussians: An Approach for Efficient Real-Time 3D Scene Reconstruction |
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Yu Du1, Ho-Pun Lam1, Ka Lok Man1, Xinyue Zhang1, Jeremy Smith2 1Xi’an Jiaotong-Liverpool University |
|
| 14:20 ~ 14:35 |
Multimodal Scene Augmentation Framework on Edge Platforms for Autonomous Driving |
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Xinyue Zhang1, Fengyufan Yang2, Yuxuan Zhao1, Erick Purwanto1, KaLok Man1, Jeremy Smith3, Yutao Yue4 1Xi’an Jiaotong-Liverpool University |
Organizers: Prof. Yoshifumi Nishio (Tokushima University, Japan)
Timetable Session Abstract
TBD
| Time | Details |
| 14:50 ~ 15:05 |
(Invited) Analysis of Class-EF Inverter Characteristic Outside Nominal Condition |
|
Shiono Tomoya, Komiyama Yutaro, Nguyen Kien, Sekiya Hiroo Chiba University |
|
| 15:05 ~ 15:20 |
Effects of Dopant Mobility of a Memristor in a Chaotic Circuit |
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Taishi Segawa, Yoko Uwate, Yoshifumi Nishio Tokushima University |
|
| 15:20 ~ 15:35 |
Hysteresis Characteristics of a Linear Memristor in van der Pol Oscillators Coupling System |
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Keizo Kubota, Yoko Uwate, Yoshifumi Nishio Tokushima University |
|
| 15:35 ~ 15:50 |
An FPGA-Based Simulator for Hematopoietic Stem Cell Dynamics based on Ergodic Sequential Logic |
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Momoka Aiba, Hiroyuki Torikai Hosei University |
|
| 15:50 ~ 16:05 |
Two-tone suppression of ergodic sequential logic FPGA cochlear model |
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Neo Ogawa, Hiroyuki Torikai Hosei University |
|
| 16:05 ~ 16:20 |
Evaluation of Genetic Algorithms Incorporating Social Behavior of Naked Mole Rat |
|
Naoki Yoshida Tokushima University |
Organizers: Prof. Shin-Chi Lai (National Formosa University, Taiwan)
Prof. Yuan-Ho Chen (Chang Gung University, Taiwan)
Timetable Session Abstract
This special session focuses on the challenges and innovative solutions in model design, quantization, control strategies, and system integration for intelligent systems and high-efficiency computing and energy applications. The five selected papers span a diverse range of technologies—from neural network quantization using QUBO modeling and quantum-inspired annealing, Transformer-based applications in language and physiological signal processing, to advanced control designs for power converters including multi-arm series capacitor and resonant topologies. These works highlight how advanced optimization methods, deep learning architectures, and simplified yet effective control schemes can enhance system performance, stability, and observability across various application domains. The session aims to foster in-depth discussion among cross-disciplinary experts on emerging trends, integration strategies, and future directions in intelligent computing and power electronic control systems.
| Time | Details |
| 14:50 ~ 15:05 |
Design of a Modular and Observable Transformer- Based Translation System |
|
WU CHEN1, Chen Yuan-Ho2, Lin Wen-Yen1 1Chang Gung University |
|
| 15:05 ~ 15:20 |
(Invited) Heart Rate Estimation from FMCW Radar Using CNN Autoencoder–Transformer for Motion Artifact Mitigation |
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Shin-Chi Lai National Formosa University |
|
| 15:20 ~ 15:35 |
Mixed-precision Neural Network Quantization with Quantum-inspired Annealers |
|
Cing-Yuan Lai1, Chin-Fu Nien2, Lien-Po Yu3, Chao-Sung Lai2 1Chung Yuan Christian University |
|
| 15:35 ~ 15:50 |
A 2.4GHz High-Efficiency GaN Power Amplifier Design Using Transmission Line Matching |
|
Chin Hsia, Kuang-Ting Cheng, Chung-Yi Li Chang Gung University |