Tutorials

Abstract
The ever-increasing processing rates of modern electronic systems necessitate high-speed analog circuits. However, a fundamental design trade-off exists between response speed—governed by bandwidth and slew rate—and power consumption. This tutorial talk delves into energy-efficient design strategies and insights to overcome this conventional trade-off in analog amplifier circuits. First, the presentation examines the direct relationship between bandwidth and effective transconductance (Gm). It highlights the power inefficiency of conventional methods for increasing Gm and introduces advanced, energy-efficient Gm-boosting techniques that break the trade-off by enabling the circuit to operate differently in large-signal (power) and small-signal (bandwidth) domains. Next, the tutorial investigates the impact of slew rate (SR), which dominates the initial transient response. The discussion focuses on SR enhancement techniques that break the static power trade-off by providing large, dynamic currents only during the slewing phase while maintaining low quiescent power. Effective methods such as tail-current boosting, super-class-AB input stages, and nonlinear current mirrors are presented as ways to maximize the SR figure-of-merit. The challenge of driving large RC loads is also addressed, with the pre-emphasis technique offered as a solution to overcome the load time-constant. The final section addresses the complexities of multi-stage amplifier design, which offers higher gain but introduces stability challenges due to multiple poles. It reviews traditional Miller compensation before introducing more advanced techniques such as current-buffered Miller compensation, hybridization, and a novel domino-buffered architecture, which demonstrates a significant extension of bandwidth and enhancement of phase margin under equivalent power constraints. Ultimately, this tutorial provides circuit designers with valuable insights and practical techniques for creating the next generation of energy-efficient, high-speed analog circuits.

Abstract
The rising demand on the Internet of Things (IoT) sensor nodes has long pushed for aggressive device miniaturization and nearly perpetual operation. Wide power-performance adaptation down to nanowatts is becoming crucial in always-on and energy-autonomous systems, which could ensure the continuous operation amidst energy/power source fluctuations.

In this tutorial, directions and techniques for aggressive extension of power-performance scalability in AIoT circuits and systems will be introduced. Silicon demonstration of battery-indifferent systems will be presented, which supports continuous operation despite the intermittent power availability. Dual-mode logic family will be introduced for standard cell reconfiguration, which allows for purely-harvested operation and extends the power-performance trade-off by three orders of magnitude. The tutorial will also cover wide-power scaling techniques for capacitive and light sensor interfaces, nano-watt energy harvesting circuits and power management units, ultra-Low power circuit design for always-on blocks (e.g., reference circuits, crystal oscillator). Circuit implementation details and silicon measurement results will be provided to offer actionable insights for circuits and systems designers interested in this topic.

Motivation and Focus
The rapid expansion of AIoT devices and energy-autonomous systems has created a pressing demand for ultra-low-power integrated circuits capable of intelligent power-performance adaptation. Conventional battery-powered designs are increasingly inadequate for applications where energy availability is unpredictable (e.g., energy harvesting) or where maintenance-free operation is critical (e.g., biomedical implants, environmental sensors). To remain functional under widely fluctuating power conditions, next-generation systems must achieve a dynamic range spanning several orders of magnitude (e.g., nW-to-mW).

This tutorial explores the key advancements in battery-less and battery-indifferent integrated systems, presenting cutting-edge circuit techniques and design methodologies for ultra-wide power-performance scalability. We cover critical components of sensor platforms, including analog frontends, sensors, digital systems, always-on circuits, energy harvesting, and power management. Key concepts are demonstrated through test chip designs and experimental results.

Aligned with ISOCC 2025’s theme, “Pioneering Heterogeneous Integration of SoCs for AI-Driven Smart Systems,” this tutorial addresses the crucial challenge of extending AIoT system longevity through ultra-low-power circuit innovations. Attendees will gain actionable insights for developing next-generation battery-indifferent SoCs, empowering researchers and engineers to advance sustainable, intelligent edge computing.

Basic Structure of the Tutorial
Section I: Background of Battery-Indifferent Systems for Ubiquitous Sensing (15 mins)
Motivations and applications of battery-indifferent miniaturized systems for ubiquitous sensing; Challenges in designing battery-indifferent systems with highly constrained size; Key specifications in both circuits and systems.

Section II: Ultra-Low Power Circuit Design for Always-On Blocks (20 mins)
Concept of duty-cycling and requirements for always-on blocks; pW-level voltage reference circuit; sub-nW crystal oscillators with adaptive pulse injection.

Section III: Power-Reconfigurable Digital Logic Circuit Design (20 mins)
Performance, power and energy tradeoff under voltage scaling; dual-mode logic and standard cell library; continuous ultra-wide range power reconfiguration in dual-mode logic.

Section IV: Wide-Power Scaling Analog Frontend Design (15 mins)
Motivation of wide-power scaling in sensor interface circuits; wide-power scaling techniques for capacitive and light sensor interface and ADC; circuit implementations and benchmarks.

Section V: Integrated Energy Harvesting and Power Management (20 mins)
Requirements and key specifications for integration of energy harvesting and power management units; multi-mode DC-DC converter design; self-startup circuit with on-chip solar cell.

Abstract
The design of ultra-low drift readout circuits for MEMS oscillating accelerometers is essential for high-precision navigation systems. This talk will cover the basic principles and application requirements of MEMS resonant sensors, followed by the development of a compact noise model to address the unique challenges of these devices. Advancements in low-noise, high-efficiency readout circuits will be explored, focusing on a phase-locked loop (PLL)-based architecture that effectively eliminates 1/f noise. A built-in data converter, with minimal hardware overhead, will also be presented. The challenges of hysteresis-free temperature compensation through in-situ quality-factor measurement will be discussed, alongside methods to mitigate noise caused by structural mismatches. Experimental results and circuit implementation details will highlight cutting-edge solutions to optimize MEMS accelerometer performance, providing key insights for sensor and systems designers.

Motivation and Focus
Microelectromechanical inertial measurement units (MIMUs) are critical components for autonomous navigation in unmanned systems. Recent advances in silicon oscillating accelerometers (SOAs) have demonstrated exceptional long-term stability, positioning them as a transformative technology for compact, satellite-denied inertial navigation in agile platforms such as drones and underwater UUVs. These applications demand ultra-low drift, miniaturized form factors, and robust performance under dynamic environmental conditions—challenges that hinge on innovations in readout circuit design, noise mitigation, and temperature compensation.
This tutorial provides a comprehensive framework for designing SOAs, spanning fundamental theory, circuit architectures, and system-level optimization. Attendees will gain actionable insights into cutting-edge techniques, including: Low-noise readout circuits; Hardware-efficient data conversion; Hysteresis-free temperature compensation; Mismatch-induced noise reduction. Tailored for researchers and engineers, the session bridges theoretical principles with practical implementation, empowering the development of next-generation inertial sensors. The content aligns with ISOCC 2025’s focus on “Pioneering Heterogeneous Integration of SoCs for AI-Driven Smart Systems” by addressing co-design challenges at the MEMS-circuit interface and enabling intelligent, autonomous navigation solutions.

Basic Structure of the Tutorial
Section I: Background and Principle of Silicon Oscillating Accelerometers (SOAs) and Its’ Key Specifications for Navigation (5 mins)
Application and the requirements of key specifications; Basic principles of Long-Term Sensors, Such as Inertial sensors for long-term navigation applications. And the equivalent circuit model for typical sensors.

Section II: Compact Drift and Noise Model of SOAs with Readout Circuits (10 mins)
Relationship drift/noise and the long-term sensing specifications; LTI noise model of a typical long-term sensory systems; Nonlinear noise path in sensors.

Section III: Design of the Low-noise High-efficiency Readout Circuits for SOAs (10 mins)
The bottle neck of existing readout circuits in the drift/low-frequency noise point-of-view; PLL-based readout circuit architecture eliminates the low-frequency 1/f noise source; Built-in data-converter with almost zero hardware overhead; Circuits implementation and benchmarks.

Section IV: Hysteresis-free temperature monitoring and compensation (10 mins)
Overview of the existing temperature compensation approaches; In-situ quality factor measurement; Quality-factor-based hysteresis-free compensation and its experimental results.

Section V: Background Structural Mismatch Compensation in Readout Circuits (5 mins)
1/f noise leakage due to structural mismatch; Background mismatch compensation and its circuit implementation; Experimental Evaluation.

Abstract
Neuromorphic computing is an innovative technology that mimics the human’s brain, offering substantial potential in energy efficiency and parallel processing. It is gaining attention as the next-generation AI semiconductor, following GPU and NPU. Just as the human brain conserves energy during periods of minimal thought, the neuromorphic computing operates on an event-based system, performing calculations only when spike signals occur, enabling low-power operation. IBM recognized this potential and developed a neuromorphic chip called TrueNorth; however, technical limitations at the time made it challenging to apply to complex tasks. Recently, advances in new algorithms capable of creating highly accurate neuromorphic neural networks have allowed neuromorphic computing to be re-applied to a variety of complex tasks. Consequently, IBM and Intel have developed new neuromorphic processors, such as NorthPole and Loihi, expanding their application potential in areas like object recognition and classification. Additionally, neuromorphic computing is now combined with deep neural networks (DNNs), proposing a new computing approach that simultaneously achieves low power consumption and high accuracy, making it possible to handle complex tasks, such as large language models, with energy efficiency. This presentation will highlight the past limitations and recent resurgence of neuromorphic computing and explore its future potential in the semiconductor industry.